Then he demonstrated how to solve a basic problem creating Verilog testbench scores. After his introductory lecture, he began to teach the participants about Creating Verilog HDL Design modules. He introduced the participants to ModelSim simulation tool. Mr Rashed kibria, lecturer (Part-time) of department of EEE, BUET was the instructor of this session. On 9 th July, 2020 IEEE EDS BUET student branch chapter organized an interactive virtual session on Introduction to FPGA prototyping, a three session long virtual workshop on Intel Altera and Xilinx FPGAs. Then he demonstrated how to solve a basic problem – how to analyze it, synthesize into small sub problems and simulate them in Quartus II software. After his introductory lecture, he began to teach the participants about Verilog HDL programming language – how it differs from other programming languages and its structure. He shared his exquisite knowledge about recent development in existing VLSI industries. The program started at 8:00 PM which was instructeded by Mr Rashed kibria, Lecturer, Department of EEE, BUET. First session was held on this day about Simulation with Quartus II. It is a three session long virtual workshop on Intel Altera and Xilinx FPGAs. On 29 th June, 2020 IEEE EDS BUET student branch chapter organized an interactive virtual session on Introduction to FPGA prototyping – INTEL ALETRA and Xilinx FPGAs (Session 1). Instructor: Rasheed Kibria, Lecturer, Department of EEE, BUET Home » Introduction to FPGA prototyping – INTEL ALETRA and Xilinx FPGAsĪ 3 session online workshop organized by IEEE EDS BUET Sutdent Branch Chapter on “Introduction to FPGA Prototyping – INTEL ALETRA and Xilinx FPGAs” for the core upliftment of the students in this long quarantine period.
0 kommentar(er)
